Interpolators

ABSTRACT

An interpolating arrangement comprises a stepper controlled to step between two computer-defined values at instants in dependence upon the difference between the values and the real time interval between the occurrence of the values. Preferably the stepper control which depends upon the real time interval is such that the stepper can step linearly between the values when the real time interval is expressed by ST in the floating-point format expression K.2(ST-1), where the expression is equal to the actual realtime interval between the occurrence of the values.

United States Patent [1 1 Eastty Nov. 12 1974 IN'I'ERPOLATORS Primarv Etaminew-Eugene G. Botz 75 In nt P ter Charles Eastt Lo (1 l vb or Eigtand n Un Attorney, Agent, or Firm-Waters, Rodin, Schwartz &

Nissen [73] Assignee: Electronic Music Studios (London) Limited, London, England 221 Filed: Dec. 21, 1973 1 1 ABSTRACT [21 Appl. No.: 427,269 An interpolating arrangement comprises a stepper controlled to step between two computer-defined values at instants in dependence upon the difference be- [30] Forelgn Apphcaumi Prmmy Data tween the values and the real time interval between Dec. 22 1972 Great Britain 59541/72 the Occurrence of the Values. preferably the stepper 1 control which depends upon the real time interval is [52] U.S. Cl. 235/152 such that the Stepper can Step linearly between the [51] Iltt. Cl. G06f 7/38 values When the tea] time interval i expressed by ST [58] Field Of Search 179/1 SA; 235/152; in the floatingpoint format expression K.2(ST-l) h 235/197 the expression is equal to the actual realtime interval 6] R f Ct d between the occurrence of the values. I

e erences e UNITED STATES PATENTS 13 Claims, 14 Drawing Figures 3349,] 80 10/1967 Coker 179/1 SA CHANGE OVER PFO q ADDER SWITCH 4 OUTPUT MEMORY 3 ADDER UWUTER I0 b 1 MEMORY 1M 6 Mi MORYPFO MEMORY 0-8 CONTROLLER SUBTRACTOR 8 2 COMPARATOR t t t t MEMORY MEMORY MEMORY COMPARATOR 2 3 4 7 TF6 MEMORY Ol n p n 0-9 t COMPARATOR to 9 -MEMORY STFO (H CLOCK CONVERTER PATEmEnuuvTzmA 3.847.349.

- SHEET 01 0F 13 AT F/GJ CHANGE-OVER PFOM ADDER SWITCH 4 OuTPuT MEMORY A T k 3 CHANGE-OVER SWITCH 5 MEMOR COMPUTER Y O-s f O 1* v MEMORY PFO MEMORY CONTROLLER SUBTRACTOR 8 2 COMPARATOR l M MEMORY -MEMORY COMPARATOR 2 4T 7 MEMORY m t COMPARATOR 1O 9 -S?;MEMORY STFOO 2 0-2 CLOCK CONVERTER COMPARATORS A B2 E8 6 A1 PATENTEDNHYIZIBM 3847349 SHEET 03 0F 13 50 0 1 A0 C 55 M S3 51 I PFOg I i 0v OVERFLOW PATENTEDNUY 12 19M sum as 0F 13 TRUE COMP SELECTOR TRUE COMP TRUE COMP \SELECT A F/c.5b

PATENTED NOV 12 I974 sum nsnr13 I PATENTEUNUV 121914 3,847,349

sum 12 or 13 FIG. 90.

0 D04 D05 D02 D01 D00 PATENTEDNUHZIQM 3 3 SHEET 13 0F 13 INTERPOLATORS BACKGROUND OF THE INVENTION This invention relates to interpolators.

In the well-known mathematical process of interpolating, points are calculated which lie between other points defining a curve or straight line. The main reason for interpolation is a requirement for more data regarding a particular curve or line. Thus, to take an example which is described more fully in an application in the name of David Cockerell, Ser. No. 427,266, filed Dec. 21, 1973, one may wish to operate a computercontrolled bank of digital audio oscillators such that a synthesized voice tone is heard to change smoothly in frequency and amplitude. If there is a relatively large gap between digitally-coded frequency and/or amplitude values the desired voice tone may, in fact, be heard as a series of discreet notes of different frequencies and/or amplitude. Clearly here is an application for interpolation, because if more digital values can be generated between the given values the discreet-note effect will be reduced. Moreover, ifa sufficient number of interpotations is performed between the given values the sound produced will be indistinguishable from a truly smoothly changing frequency and/or amplitude tone because the human ear is incapable of telling the difference between a truly smooth variation and a stepped variation, provided that the steps are small enough.

DISCUSSION OF THE DISCLOSURE According to the invention there is provided an interpolating arrangement comprising:

stepping means for interpolating in small steps from an initial value, said stepping means having a control input for receiving signals to initiate respective ones of said small steps;

comparison means having first input means available to receive a reference value dependent upon a predefined real-time duration of an interpolating operation from said initial value to a further value, second input means and an output for transmitting for said stepping means a possibly step-initiating signal when said comparison means senses a predetermined relationship between the values of signals at said first input means and said second input means of said comparison means; and

signal generator means connected to said second input means of said comparison means and being operable to generate a succession of values repeatedly during said predefined duration of said interpolating operation.

Preferably, the values of said succession are such that the comparison means will emit said signals, if at all, at equal intervals of time whatever the reference value. This feature enables the interpolation between the two values to be linear interpolation, provided that the small steps are equal in magnitude.

Preferably the comparison means is arranged to receive said reference value in the form of a parameter in a predetermined function representing the length of said real time duration, and preferably the values in said succession are such that the frequency of said signals from the comparison means will be inversely proportional to the length of said real time duration when the reference value is received by the comparison means as said parameter.

preciated more fully where said reference value is the parameter ST in the function K- Z representing the length of said real time interval. Here the signal generator is designed such that the values in the succession generated by it will represent the number of the most significant digit last to change in a binary digital count performed in the signal generator and sampled at a predetermined frequency. Said predetermined relation ship will then be that the individual value in said succession 2. ST. The form KZ is particularly advantageous because, firstly, the value of the function as a whole can have a wide possible range of values for a relatively narrow range of values of ST, which provides an economical use of computer storage. Moreover, this particular form of function is advantageous for computer programming techniques, the particular form being known as floating-point format.

BRIEF DESCRIPTION OF THE DRAWINGS For a better understanding of the invention and to show how the same may be carried into effect reference will now be made, by the way of example, to the accompanying drawings in which:

FIG. 1 shows a portion of a straight line two points on which are defined by digitally coded computer output signals;

FIG. 2 shows a simplified circuit diagram of a first embodiment of interpolating arrangement according to the present invention;

FIG. 3 shows a block circuit diagram of the first embodiment;

FIGS. 40 to 7b show in detail the circuitry of respective blocks of FIG. 3;

FIG. 8 shows a block circuit diagram of a second embodiment of interpolating arrangement according to the present invention; and

FIGS. 9a and 9b show in detail the circuitry of a block of FIG. 8.

DETAILED DESCRIPTION OF THE DRAWINGS FIG. 1 shows a portion of a straight line on which two points PFO (the present value) and AFO (the aiming value) are two adjacent points. The line is a plot of frequency F against time t in the present case, although it could be of amplitude A against time t. AT is the real time interval between the occurrence of the values PFO and AFO.

Digital computer output signals, in real time, defining frequency and amplitude values can be used to control the output signals of a bank of oscillators to produce, for example, a voice tone of variable frequency and amplitude. An arrangement utilising such oscillator control is described in our co-pending Application corresponding to British Pat. application No. 59540/72 and entitled Waveform Processing. The two embodiments of interpolator described hereinafter are, in fact, utilised in the system described in the co-pending patent application and it may help the reader of this specification to refer to the other application in order to get an idea of the overall plan of a system in which the present interpolators can be utilised, also to trace the origins of certain signals, such as timing signals, as will be referred to in the present description. The interpolators are used to interpolate between values of frequency and amplitude defined by the computer as described in the co-pending application. It will be appreciated that it is better to have a large number of small frequency and amplitude steps than a small number of large steps, because the former produces smoother changes in voice tone and amplitude to someone listening to the synthesized sound. Thus the interpolators are to slew between the pre-defined values of frequency (and amplitude) in a predefined real time interval AT.

FIG. 2 shows in simplified form the circuit of the interpolating arrangement for interpolating linearly between frequency'values PFO and AFO in the actual slew time AT. A memory (not shown in this Figure for the sake of simplicity) feeds the present value PFO in the form of a 10-bit digital word PFC to the upper input of an adder l. The lower input of adder 1 carries either a positive or negative signal in dependence upon whether AFO is greater or smaller than PFO. The adder 1 interpolates between PFO and AFO by steps of constant magnitude equal to the least significant bit of PFO The frequency of stepping of adder 1 depends upon a controller 2 (as is described more fully hereinafter) and the steps are incremental or decremental depending upon the polarity at the lower input of the adder 1. When decremental steps occur the adder 1 adds steps of 1 to the value PFO Stepping values from the adder l are fed to an output 3 of the arrangement and tothe memory through a change-over switch 4 which is usually in its upper, shown, position to feed interpolations to the output 3 when the arrangement is operational. Each newly stored stepping value from the output 3 replaces PFO at the upper input of the adder 1 for the next interpolation so that PFC-:1 can next be stepped to PFC-:2 and so on.

Also connectable to the output 3 through the changeover switch 4 is a further change-over switch 5. When switch 4 is in its lower position and switch 5 in its lower position the output 3 will be connected directly to a computer output LAL carrying a nine-bit digital word I defining the aiming point AFO. The interpolator is, effectively, by-passed by this particular connection. The reason for this facility will become apparent later. An adder 6 feeds into the upper contact of the change-over switch and receives the input I from the computer and also an eight-bit word PFO defining the present value from the memory. Again the reason for this will become apparent later.

A subtractor 8 is connected to receive the input 1 from the computer and also PFO from the memory at the beginning of the slew cycle. The subtractor 8 calculates DFO, the difference frequency between the present and aiming frequency values, PFO and AFO, and feeds it into the memory as a 10-bit word DFI The controller 2 initiates steps of the adder 1 at a frequency depending upon two comparators 7 and 9. The comparator 7 compares the difference value DFO, in the form of a 10-bit word DFO from subtractor 8 via the memory, with a random number generated within the comparator 7. The value of DFO fed into comparator 7 does not change throughout the slew cycle between PFO and AFO. The comparator 9 compares a log frequency slew time word STFO with individual values in a succession of values produced by a signal generator in the form of a clock converter 10. The succession is fed to the comparator 9 as a varying four-bit Word RTO 3. I

The reasons for these comparisons and the theory behind them is set out below.

First, consider the clock converter 10 (its detailed circuitry is described later). Suppose a counter C is clocked to count-down at l/t counts per second.

On reaching zero the counter re-sets to a gross time value T and continues to count down to zero again, repeating the cycle of operations continuously. The counter undergoes l/Tt resets per second.

If the reset pulses are applied to a binary counter of N flip-flops E E E carrying out an N-bit count the general flip-flop (and thus bit) E changes state I/Tt'Z times per second. At regular intervals of B seconds the state of this counter is examined and compared with its state at the previous examination time B seconds previously. By suitable gating in the clock converter 10 the binary number RT is generated corresponding to the number of the greatest significance flip-flop E which has changed state since the previous examination. Thus, the probability of the general flipflop E having changed state in B seconds is B/(TI-Z and the probability of RT having a value greater than or equal to n for any given examination is also B/Tt-2"').

The number RT appears at the output of the clock converter 10 as a four-bit word RT and is continuously compared to a value ST which is called the log slew time since ST is defined by the relationship AT=K-2 in terms of AT the actual slew time interval in real time and K, known as the slew factor. It is advantageous to have in the computer the log value ST rather than the actual value AT of slew time because, in this way, it is possible to accommodate a relatively wide range of AT in a small number of bits of ST, a log value, and also because it is convenient for computer langauge pruposes to have the slew time in the form K 2 known as floating-point format. ST to produce a pulse as the output signal 2' of the comparator 9 when RT z ST Thus, if the proba' bility of Z equalling 1 for an individual examination is P then P 1 equals B/[Tt-2 except for where ST=0, in which case P =1.

The first few values in the succession of RT are shown in FIG. 2 at the output of clock converter 10 and it can be seen that, as ST decreases linearly the frequency of pulses from the comparator 9 will increase logarithmically to the base 2. In other words, as the desired slew time decreases, the frequency of pulses rises as the antilog to the base 2 of ST-1. Also, it will be noted that these pulses would equally be spaced in time for providing the linearity of the slew.

Considering now comparator 7, it compares the difference value DFO between PFO and AFO with an internally generated random number. In fact, this number is not random in the sense that its next value cannot be predicted, but in the sense that its possible values are arranged in a random, yet fixed, order. This number is the reverse of a digital count. Thus, for instance, while the first three numbers of a four-bit count are 0001, 0010, and 0011, the first three numbers of the reverse of the count would be 1000, 0100, and 1100, being numbers which are randomly distributed in value but nevertheless predictable in order. Because of this predictable feature of its nature the number shall hereinafter be called pseudo-random and shall be given the designation J.

The difference value DFO is compared with J at predefined intervals of B seconds (J and DFO both lying in the range 0 to 2) and the output signal Z" of the comparator 7 becomes a pulse when D J. Thus, if the possibility of Z equalling 1 is P then P =D/2" (J being random) If the controller 2 is a logic gate (an AND gate for example) having input signals Z and Z" it thus has a probability P of having a one-signal as its output signal Z (ignoring for the moment the effect of comparator 11) such that m 2(sTn Both the present value PFO and the aiming value AFO have maximum values of 2'". PFC is incremented or decremented (depending upon the polarity of the signal at the lower input of adder 1) by a step of l at each interval of B seconds if Zis l for that interval, and is not stepped if Z is 0.

Thus, the rate of change of the output data of the interpolator is:

DF0/[2'"Tt'2 steps per second.

The actual time AT taken for the value PFO to be I stepped to AFO is thus given by:

It will be noted that AT is independent of the absolute values of PF 0 and APO and that PFO changes linearly with respect to time to the new value because; a) although ST is a log value the pulse frequency from comparator 9 is inversely proportional to the antilog of ST; and b) the pulse frequency from comparator 7 is directly proportional to the difference value DFO.

The interpolation value at any instant PF 0+ [DFOXtime elapsed/T-ztsr- The comparator 11 effects a simple magnitude comparison between PFO and AFO to block the controller 2 from emitting more step-initiating pulses when PFO has been increased to AFO and before a new aiming point AFO is defined by the computer.

A brief explanation of normal operation of the FIG. 2 arrangement will now be given. It will be assumed that the computer has just produced an output signal fed into the interpolator as 1 defining a new aiming point AFO and that the value present at the upper input tothe adder l and at the output 3 is PFO. The arrangement is therefore just about to begin slewing between PFO and .AFO.

When the adder 1 receives a pulse from the controller 2 the output word PFX from the adder 1 becomes equal to PFO i 1 depending upon the polarity at the lower input of adder 1, which in turn depends upon whether the computer defines AFO as greater or smaller than PFO. If this polarity is negative a ls compliment function is performed to subtract the l. The output signal PF X of the adder l is applied to the output 3 and to the memory via the change-over switch 4. One interpolation step is complete and the value PFX replaces PFO in the memory and. when the controller 2 next orders an interpolation step it will take place from the value of the original PFO i l. The interpolation steps will then continue, in dependence upon controller 2, until the aiming point AFO is reached. The controller 2 will then be blocked by comparator 11 until a new aiming point AFO is defined by the computer.

The increment and decrement in PFO at each interpolation step is constant. It is the timing of the interpolations, dependent upon controller 2 as described, which drives the value of the output 3 linearly towards AFO.

In normal interpolating operation such as has just been described the output 3 is connected to adder 1 through the upper path of change-over switch 4. It is possible, however, for the computer output to bypass the adder 1 and to send to the output 3 directly a new aiming point different from the presently aimed-for point AFO. This is done firstly by putting change-over switch 4 into its lower position to connect the output of change-over switch 5 to the output 3. The computer can define this new aiming value in two ways: either absolutely, in which case the switch 5 is put into its lower position to send I directly to output 3; or by the difference between AFO and the new aiming value, in which case the switch 5 is put into its upper position and receives AFO 11 from adder 6 depending upon whether the new aiming value is above or below AFO. The output of switch 5 is also connected to the memory to feed the new aiming value to it as AFI FIG. 3 is a block circuit diagram of a preferred embodiment of the frequency interpolator shown in sim- I plified form in FIG. 2. In fact, this particular embodiment is employed in the arrangement described in, the aforementioned co-pending application to slew oscillator bank frequency values.

The seven blocks in FIG. 3 represent seven circuit boards and the interconnections between them are shown. In the co-pending application this Figure is also shown and the upper three blocks are referenced 18 while the next three blocks are referenced 19. In the present FIG. 3 on the other hand, numerals l2 and 13 designate circuit boards constituting a frequency slew calculator and numeral 14 designates a frequency slew operator board. Blocks 15, 16 and 17 are three identical READ and WRITE main memory boards constituting the memory referred-to, but not illustrated, in FIG. ll.

We are not concerned here with the detailed internal circuitry of the memory boards 15, 16 and 17, nor with control and other inputs to them which do not assist in the understanding of the interpolator per se. If a deeper understanding of the memories 15 to 17 is desired however, reference can be made to the aforementioned copending patent application. Moreover, the interconnections between the separate boards of FIG. 3 are evident from the figure itself and no further discussion of them is considered necessary since FIGS. 4 to 7 show in detail the circuitry of the different boards of FIG. 3 with their input and output terminals. It is, however, just necessary to mention that corresponding memory inputs and outputs are designated U and V respectively. Thus, the difference frequency DFI calculated in block 12 is read into memory 15 as U and is read out as V and V from the same memory. Similarly with U 11 and V 11 and the other data inputs and outputs to the other two memories 16 and 17.

It should be mentioned at this stage that substantially all the circuitry of the interpolator is in the form of commercially available digital integrated circuits.

Those actually utilized are manufactured by Texas Instruments and a key indicating that companys own reference numerals for the particular circuits will hereinafter be given after the introduction to each of FIGS.

4 to 7 (and later FIG. 8). Also given on the Figures, where significant, are the various pin designations for the integrated circuit packages.

E11 is a gatingblock SN 7420 E12 is a comparator block SN 7485 E13 is a counter block SN 7497 The adder 1 of FIG. 2 is constituted by blocks E1 to E7 in FIG. 4. The blocks E1 to E3 read out from memory 15 the 10-bit word PFO defining the present value, and the positive or negative signal ordering incremental or decremental steps is provided as DFX When DFX is positive the adders E1 to E3 add a onebit to PFO at each interpolation step and when DFX is negative the adders E1 to E3 effectively subtract at each step by a is complement operation.

Interpolation steps are ordered bythe gate block E11 (constituting the controller 2 of FIG. 2) which controls the data selector blocks E5 to E7. When there is no step order from E11 the selector blocks E5 to E7 connect those outputs of the circuit board which provide PFX the stepped value, to receive PFO directly from the left-hand of the board. When a step is ordered, however, selectors E5 to E7 change-over and supply as PFX the word appearing on the outputs of the blocks E1 to E3, which is PFO i 1. This new value PF X is read into a memory 16 via board 13 (as will be described) and replaces the original valueof PFOM at the left-hand inputs of board 15. In the meantime the selector ES to E7 has changed back so that it still receives PFX but this time from the board inputs, and is awaiting the next step order whereby the new step signals PFX i 1 (equals original PFO 2) can be selected from the outputs of blocks E1 to E3.

clock converter 10. E12 enables the lower NAND gate of block E11 when RT 2 STFO by virtue of the connections indicated along the bottom edge of block E12.

The comparator 11 of FIG. 2, which blocks controller 2 when PFO has been advanced as far as AFO is constituted by three comparator blocks E8 to E10.

FIG. 5 shows details of the frequency slew calculator board 12 of FIG. 3.

E1 is an arithmetic function unit block SN 74181 E4 is a carry block SN 74182 E5 is a true/complement block SN 741'187 E8 is a gating block SN 7437 E9 is a selector block SN 74157.

Blocks E1 to E3 constitute the subtractor 8 of FIG. 2 and block E4 provides a carry facility for the arithmetic operation.

As was mentioned with respect to FIG. 2 the input data 1 from the computer can define the aiming value in two ways: either absolutely or by the difference between two values. If the latter is the case the difference will be equal to AFO-PFO at the beginning of the slew operation. In this case the difference value DFI will actually be read into the blocks E1 to E3 at the beginning of the slew operation. It will thus be unnecessary to perform any subtraction on the incoming computer signal I In this case an appropriate signal RF will control the selector block E9 to cause subtractor blocks E1 to E3 and blocks E5 to E7 to provide straight-through paths for the input data from the computer.

If, on the other hand, I expresses AFO absolutely the signal RF will be different and will cause the selector block E9 to switch blocks E1 to E3 to their subtract mode and blocks E5 to E7 to their compliment mode. In this case blocks E1 to E3 will form the function A-B-l (A and B referring to the input letters for those blocks), putting the differences values AFO-PFO in 2s complement form. The complement blocks E5 to E7 subsequently change this form to magnitude and sign form, the magnitude value being carried by bits DFI and the sign by DFI, It is to be noted that DFI iscalculated once only in every slewing operation and is not re-calculated each time PFO steps towards the aiming point. This is because the value DFI, which is read into memory 15 of FIG. 3, is read out of the memory 15 to provide the fixed difference value DFO fed into blocks E13 and E14 of FIG. 4.

FIG. 6 shows details of the frequency slew calculator board 13 of FIG. 3.

Each of blocks E1 to E3 is an SN 7481 Each of blocks E4 is an SN 7437 Each of blocks E5 E10 is an SN 74157 Each of blocks E11 is an SN 74185.

Blocks E1 to E3 constitute the adder 6 of FIG. 2 and block Ell provides a carry facility. It will be remembered that the adder 6 is used when it is desired to send the output of the interpolating arrangement directly to a new aiming point at some instant in the course of a slew between a previous PFO and the AF 0 value which is to be changed, and when the computer output 1 defines AFO in terms of the difference between the old and new aiming values. When the computer output I defines a new aiming point directly the adders E1 to E3 can be bypassed. Thus, selector blocks E to E7 have one set of inputs connected to receive I directly and another set connected to the inputs of the adder blocks E1 to E3.

The blocks E5 to E7 constitute the change-over switch 5 of FIG. 2 and are controlled by an input signal R17. The blocks E1 to E3 can add or subtract 1 and AFC in dependence upon the bit I which is a sign bit indicating whether the new aiming point is greater or smaller than AFO. The top input bit LFI to block E5 is provided because there is no corresponding bit I in the signal from the computer.

The blocks E5 to E7 supply the new aiming point either directly as I or, after addition, AFO i I as appropriate to memory 17 as AFI and to further selector blocks E8 to E111 constituting the change-over switch 4 of FIG. 2. These blocks are controlled by signal R18 and can supply PFI the output of the interpolator, either from PFX the output of the circuit board shown in FIG. 4, or via the blocks E1 to E3 and E5 to E7 as just described.

Block 4 in FIG. 6 provides a number of gates three of which are controlled by I the sign bit of the data from the computer, and the fourth of which produces DFX from DFO the sign bit of the difference frequency between DFO and AFO. DFX is used to control the adder blocks E1 to E3 in FIG. 4.

FIG. 7 shows details of the clock converter of FIGS. 3 and 2.

Each of E1 to E4 is an SN 74l6l Each of E5 to E12 is an SN 7495 Each of E and E16 is a 9318 E18 is an SN 7495 A clocking pulse RTI, the frequency of which depends on the slew factor K, is applied to a 15-bit counter comprising counter blocks E1 to E4. This counts-down into a buffer comprising four register blocks E5 to E8 and from there into a further buffer comprising four further register blocks E9 to E12. The buffer blocks E5 to E12 are enabled at periodic inter vals by a constant frequency clock signal C20. The blocks E5 to E8 therefore, on being clocked, take in at a particular value of the count from blocks E1 to E4 and put this value on the pins between blocks E5 to E8 and E9 to E12. At the next pulse C this particular value is transferred from these intermediate pins to the output pins of the blocks E9 to E12, whilst a fresh value of the count is put on to the intermediate pins. The two digital words at the inputs and outputs respectively of blocks E9 to E12 are now compared with one another to find out which bits, if any, changed in the period be tween the two preceding clock pulses C20. This is done by connecting the output pins directly to fifteen OR gates E13 respectively, together with the intermediate pins through 15 inverters E14. The signals at the outputs of the OR gates E13 indicate whether or not the respective bits have changed, and these signals are applied to two priority encoder blocks E15 and E16 which supply, via NOR gates E17 and a buffer block E18, a four-bit word RT which represents the number of the greatest significant bit of the count performed by blocks E1 to E4 to have changed between the preceding two successive clock pulses C20. RT is fed from the clock converter to comparator block E12 of FIG. 4 for comparison with the log frequency slew time STO The values of the greatest significant bit to change in the count performed by blocks E1 to E4 form the succession 1,2,],3, 1,2, 1,4 etc. Since the count is a15- bit count this succession will contain a considerable amount of numbers before the count is completed. An initial few values of this succession is shown in FIG. 2.

Between the values in succession occur 0 values. In fact, the length of the 0 values depends upon the relative frequencies of the clock pulses C20 and RTI. The slower RTI, the longer will be the 0 values because the bits of the count will change less frequently with respect to C211. Thus, the slower RTI the more drawn out in real time the succession becomes and the slower the pulse frequency out of comparator 9. Gn the other hand, the faster RTI becomes the more compressed be comes the succession and, eventually, the 1 values, then the 2 values etc., will disappear from the succession as more and more counting steps take place between successive clock pulses C20 It will be appreciated, however, that certain unique properties of the succession are retained even upon its extension or compression. Thus, when RT is compared with ST, as ST decreases the frequency at which RT is ST increases as the antilog to the base 2 of ST. Moreover, the instants at which RT 2 ST will occur at equal intervals in time.

FIG. 8 is the block circuit diagram of another embodiment of interpolating arrangement as utilised in the embodiment described in the aforementioned copending patent application. This interpolator is somewhat simpler in construction than the preceding one, and is used to interpolate between computer-defined amplitude values.

Each of blocks E1 and E2 is an SN 74181 Each of blocks E3 and E4 is an SN 74H87 E5 is an SN 7486 E6 is an SN 74157 E7 is an SN 7485 E8 is an SN 7425 E9 and E10 is an SN 7485 E11 is an SN 7497 E12 and E13 is an SN 74181.

Block 18 represents a circuit board carrying an amplitude slew computer and operator. In the aforementioned co-pending patent application this block has the reference numeral 23. Blocks 24 of the co-pending application are numbered here as blocks 19 and 20 and represent memory circuit boards. Block 21 here is another clock converter and has the same circuitry and operation as clock converter 10 shown generally in FIGS. 2 and 3 and in detail in FIG. 7. Each of the memories 19 and 20 is the same as each of the memories 15, 16 and 17 of FIG. 3 and, again, details of these circuits will be found in the co-pending application; the present description will be limited to a discussion of the circuitry in block 18, although the interconnections be tween blocks 18 to 21 will be apparent from FIG. 8.

FIG. 9 shows the detailed circuitry of the block 18 in FIG. 8, and the components key is set out above immediately after the introduction to the description of FIG. 8.

Many similarities can be seen between the circuitry of FIGS. 4 to 7 on the one hand and FIG. 9 on the other, although the circuitry of FIG. 9 is somewhat simpler than that of the frequency slew calculators and operator. There is thus no circuitry providing corresponding components for the change-over switches 4 and 5 or the adder 6 of FIG. 2.

In FIG. 9 the present value P is read into adder blocks E12 and E13 where it is incremented or decremented, a step at a time, and read out as J A signal D06 determines, via an exclusive OR gate E5, whether the blocks E12 and E13 are to increment or decrement depending upon whether the aiming value is greater or less than the present value. The adder blocks E12 and E13 have a similar function to the adder block 1 of FIG. 2.

The actual stepping instants of adder blocks E12 and E13 of FIG. 9 depend upon a NOR gate block E8 which controls output pulses from the block E5 and which corresponds to the the controller 2 of FIG. 2.

The mathematical theory between the timing of the interpolations is exactly the same for the frequency and amplitude slew operators. The block E8 receives inputs from a comparator block E11 which generates internally a pseudo-random number, in the same way as do the blocks E13 and E14 of FIG. 4, at a frequency determined by a clock signal C8 generated externally of the interpolator. This pseudo-random number is compared with the difference amplitude DO between the present and aiming values of amplitude.

A further comparison block E7 compares the log amplitude slew time STO with RT a four-bit number changing to provide succession 1, 2, 1, 3, etc as described with reference to FIG. 7. RT is generated by a further clock converter 10. Block E7 does not feed into block E8 directly: when RT 2 STO a pulse is sent from the A B output of block E7 to enable block E11 via its strobe input.

Comparator blocks E9 and E10 compare the magnitudes of the amplitude present value and aiming value, causing blocks E12 and E13 to stop stepping when the present value P equals the aiming value A The actual difference between the present and aiming values of amplitude is calculated in subtractor blocks E1 and E2 which calculate this difference in 2s complement form. This is converted to magnitude and sign form in blocks E3 and E4 and read into memories 19 and 20, from where it is fed to comparator block E11 in inverted form DO for the comparison between the difference value and the pseudo-random number. DO is a fixed value calculated at the beginning of the slew cycle and equal to the difference between the initial present value and the aiming value for the slewing cycle.

A multiplexer block E6, controlled by an externally generated signal R connects D6 (providing the sign of D to the upper right-hand pin of block E3 and also connects L either to I or L0 as desired.

When L is connected to I a memory loading operation is initiated and the block E8 is inhibited to prevent slewing whilst the memories 19 and 20 are being addressed.

When L0 is connected to L, L0 can either be a zero to enable E8 and the memory for normal interpolating operation, or a l to inhibit E8 whilst the input data 1 addresses the memory.

To ascertain in more detail the various input and output connections of the circuit diagrams set out in the drawings, reference should be made to the figures of the aforementioned co-pending application in which will be found the various connections shown in the figures of the present application. In order to ascertain the precise mode of functioning of the digital integrated circuit blocks reference should be made to a suitable catalogue published by Texas Instruments. Where necessary, allowance must be made for the fact that the various pin designations and numbers given in the specification and shown on the accompanying drawings were up-to-date in the latter part of the year 1971. Changes in these designations and numbers may have been made between that time and the time at which this specification is studied.

I claim:

1. An interpolating arrangement comprising:

stepping means for interpolating in small steps from an initial value, said stepping means having a control input for receiving signals to initiate respective ones of said small steps;

comparison means having first input means available to receive a reference value dependent upon a predefined real-time duration of an interpolating operation from said initial value to a further value, second input means and an output for transmitting for said stepping means a possibly step-initiating signal when said comparison means senses a predetermined relationship between the values of signals at said first input means and said second input means of said comparison means; and

signal generator means connected to said second input means of said comparison means and being operable to generate a succession of values repeatedly during said predefined duration of said interpolating operation.

2. An interpolating arrangement as claimed in claim 1, wherein said signal generator means is adapted so that said values in said succession are such that said comparison means will transmit possibly step initiating signals, if at all, at equal intervals of time whatever said reference value.

3. An interpolating arrangement as claimed in claim 2, wherein said comparison means is adapted to receive said reference value in the form of a parameter in a predetermined function representing said predetermined duration of said interpolating operation and said signal generator means is adapted so that said values in said succession are such that the frequency of said possibly step-initiating signals transmitted by said comparison means will be inversely proportional to said predetermined duration of said interpolating operation when said reference value is received by said comparison means as said parameter.

4. An interpolating arrangement as claimed in claim 3, wherein: said comparison means is adapted to receive said reference value at a parameter ST in a function K'2 representing said predefined duration of said interpolating operation; said signal generator is such that said values in said succession will represent the number of the most significant digit which was last to change in a binary digital count performed and sampled in said signal generator means; and said predetermined relationship being that the individual value in said succession ST.

, 5. An interpolating arrangement as claimed in claim 4, wherein said signal generator means comprises four counting elements, one per digit, such that the maximum possible value of said number is fifteen, and said 

1. An interpolating arrangement comprisiNg: stepping means for interpolating in small steps from an initial value, said stepping means having a control input for receiving signals to initiate respective ones of said small steps; comparison means having first input means available to receive a reference value dependent upon a predefined real-time duration of an interpolating operation from said initial value to a further value, second input means and an output for transmitting for said stepping means a possibly step-initiating signal when said comparison means senses a predetermined relationship between the values of signals at said first input means and said second input means of said comparison means; and signal generator means connected to said second input means of said comparison means and being operable to generate a succession of values repeatedly during said predefined duration of said interpolating operation.
 2. An interpolating arrangement as claimed in claim 1, wherein said signal generator means is adapted so that said values in said succession are such that said comparison means will transmit possibly step initiating signals, if at all, at equal intervals of time whatever said reference value.
 3. An interpolating arrangement as claimed in claim 2, wherein said comparison means is adapted to receive said reference value in the form of a parameter in a predetermined function representing said predetermined duration of said interpolating operation and said signal generator means is adapted so that said values in said succession are such that the frequency of said possibly step-initiating signals transmitted by said comparison means will be inversely proportional to said predetermined duration of said interpolating operation when said reference value is received by said comparison means as said parameter.
 4. An interpolating arrangement as claimed in claim 3, wherein: said comparison means is adapted to receive said reference value at a parameter ST in a function K.2(ST 1) representing said predefined duration of said interpolating operation; said signal generator is such that said values in said succession will represent the number of the most significant digit which was last to change in a binary digital count performed and sampled in said signal generator means; and said predetermined relationship being that the individual value in said succession > or = ST.
 5. An interpolating arrangement as claimed in claim 4, wherein said signal generator means comprises four counting elements, one per digit, such that the maximum possible value of said number is fifteen, and said first input means has a three bit input for receiving ST so that the maximum possible value of ST is seven.
 6. An interpolating arrangement as claimed in claim 1, and comprising logic circuit means coupled to said control input of said stepping means and to said comparison means, there being a further signal generator, also coupled to said logic circuit means, for generating pulses in dependence upon the difference between said initial value and said further value so that said stepping means can receive signals at said control input from said logic means at instants depending upon both said comparison means and said further signal generator.
 7. An interpolating arrangement as claimed in claim 6, wherein said logic circuit means comprises an AND gate and said further signal generator comprises a random numbers generator, said further signal generator being adapted to emit a pulse to said AND gate whenever said difference between said initial value and said further value is greater than the random number generated at a particular instant in said random numbers generator.
 8. An interpolating arrangement as claimed in claim 7, wherein said random numbers generator is adapted to perform a reverse digital count to provide said random numbers.
 9. An interpolating arrangement as claimed in claim 1, and comprising inhibiting means for inhibiting the supply of signals to said control input of said stepping means when an interpolated value becomes equal to said further value.
 10. An interpolating arrangement as claimed in claim 1, wherein said stepping means comprises adding means arranged to change an interpolated value by a constant step amount each time said stepping means receives a signal at said control input.
 11. An interpolating arrangement as claimed in claim 1, and comprising a by-pass path which can be used to by-pass said stepping means for changing the output signal of said interpolating arrangement directly from said initial value to said further value.
 12. An interpolating arrangement as claimed in claim 1, and comprising means for changing an interpolated value directly to a new further value at an instant at which said interpolating arrangement is performing interpolations from said initial value to said further value.
 13. An interpolating arrangement as claimed in claim 1, in combination with a computer programmed to provide said reference value dependent upon said predefined duration of an interpolation operation, and to provide the relative values of said initial value and said further value. 